In many modern electronic systems, such as, for example, communication transceivers, radar systems, test instrumentation and broadcasting systems, Direct Digital Frequency Synthesizers, DDFS, are an important component.
DDFSs can provide rapid frequency switching in small frequency steps, and can also provide linear phase and frequency shifting with a high degree of spectral purity.
A common DDFS architecture is one which is based on a phase accumulator in series with a phase-to-sinusoid amplitude converter. Such a DDFS usually uses two inputs: a clock reference and a frequency control word, FCW. The phase accumulator in the DDFS integrates the value of the FCW on every clock cycle, producing a ramp whose slope is directly proportional to the FCW.
The frequency of this ramp, which is also the output frequency of the synthesizer, is given by the expression:
                              f          out                =                  FCW          ×                                    f              0                                      2              w                                                          (        1        )            where:                f0 is the frequency of the clock reference, and        W is the width of the accumulator in bits.        
The phase accumulator contents can be interpreted as a portion of rotation around a unit circle, and an approximate sinusoid amplitude of the corresponding angle is produced by the phase-to-sinusoid amplitude converter.
One way of implementing the phase-to-sinusoid amplitude converter is as a ROM look up table, an LUT. In order to satisfy frequency resolution requirements in the DDFS, a wide phase accumulator is often desired. However, this leads to a very large LUT as a converter, since the number of bits the LUT contains is equal to 2N×(L+1), where L+1 is the output word length of the converter, including a “sign bit”.
One step towards reducing the LUT size is to reduce the number of entries in the table by exploiting the quadrant symmetry of the sine function. For further reduction, there are several alternatives to the ROM LUT, such as angular decomposition, sine amplitude compression, and the use of Coordinate Rotation Digital Computers, CORDIC, as well as polynomial approximations. The principle of these techniques is to trade computational complexity for ROM storage.
One of the main performance parameters for the phase to amplitude converter of the DDFS is the so called Spurious Free Dynamic Range, the SFDR. In the frequency domain, the SFDR represents the difference in amplitude or power between the generated sinusoid and the greatest undesired spectral component.
SFDR can also be a significant parameter for sensitivity and anti-interference performance in many applications. However, in known systems, a satisfactory SFDR is obtained at the price of high circuit complexity, for example in terms of storage need and the amount of computational power needed.